Analysis of the subthreshold CMOS logic inverter

AbstractThere is no doubt that operating the MOSFET transistor in the subthreshold region, where the power-supply voltage is less than the threshold voltage, has an increasing importance due to the reduced power consumption. In this paper, the analysis of the CMOS logic inverter in the subthreshold region is addressed quantitatively with the static and dynamic characteristics investigated and compared with that operating in the superthreshold region. Specifically, compact-form equations are derived for the output-low voltage, output-high voltage, maximum-input voltage at logic “0,” minimum-input voltage at logic “1,” and threshold voltage of the inverter. Also, the static-power consumption and dynamic-power consumption are investigated and equations are derived for them. Compact-form expressions are derived for the low-to-high and the high-to-low propagation delays along with the fan-out. Qualitative discussions are also provided. The results of the quantitative analysis are verified by comparison with the simulation results adopting the 65nm CMOS technology

Analysis of the subthreshold CMOS logic inverter

There is no doubt that operating the MOSFET transistor in the subthreshold region, where the power-supply voltage is less than the threshold voltage, has an increasing importance due to the reduced power consumption. In this paper, the analysis of the CMOS logic inverter in the subthreshold region is addressed quantitatively with the static and dynamic characteristics investigated and compared with that operating in the superthreshold region. Specifically, compact-form equations are derived for the output-low voltage, output-high voltage, maximum-input voltage at logic “0,” minimum-input voltage at logic “1,” and threshold voltage of the inverter. Also, the static-power consumption and dynamic-power consumption are investigated and equations are derived for them. Compact-form expressions are derived for the low-to-high and the high-to-low propagation delays along with the fan-out. Qualitative discussions are also provided. The results of the quantitative analysis are verified by comparison with the simulation results adopting the 65 nm CMOS technology. Keywords: CMOS logic inverter, Power consumption, Propagation delay, Quantitative analysis, Subthreshold region, Voltage-transfer characteristic

A novel high-performance time-balanced wide fan-in CMOS circuit

There is no doubt that static complementary CMOS logic is one of the most dominant logic-circuit families available. However, CMOS circuits with wide fan-in suffer from a relatively poor performance that is apparent in increased area, large time delay, and large power consumption. This is typically the case with CMOS circuits containing NMOS or PMOS stacks (i.e. branches containing a relatively large number of serially connected transistors). In this paper, a novel circuit that depends on applying the input signals in the form of pulses with a certain width will be presented as an alternative to stack circuits. The proposed scheme will be investigated quantitatively with the effect of the pulse width on the performance of the proposed scheme taken into account. The proposed scheme will be compared with the conventional CMOS logic from the points of view of area, high-to-low propagation delay, and average power consumption. The parameter variations and second-order effects will also be taken into account. Simulation results verify the correct operation of the proposed scheme and that the percentage reduction in the average propagation delay is 15.8% and 61.25% in cases of four and eight inputs, respectively, adopting the 45 nm CMOS technology with VDD = 1 V

Understanding the behavior of RTD-loaded NMOS inverter through compact-form analysis

Resonant-tunneling diodes (RTDs) find a wide variety of applications in oscillators, digital circuits, and latches due to their reduced circuit complexity, low power, and high speed. Since the inverter is the main building block in digital design, in this paper, the analysis of the RTD-loaded NMOS inverter is addressed quantitatively with its static and dynamic characteristics investigated and compared with that of the conventional static CMOS inverter. Specifically, compact-form expressions are derived for the critical points of the voltage-transfer characteristics (VTC), the low-to-high, and the high-to-low propagation delays along with the fan-out. Also, the static- and dynamic–power consumption are investigated and equations are derived for them. The results obtained from this analysis can be generalized to RTD-MOS logic-circuit family in which the pull-down network contains properly connected and appropriately sized NMOS transistors and the pull-up network is the RTD device. The results of the quantitative analysis are discussed and verified by comparison with the simulation results using the Berkeley predictive-technology model (BPTM) of the 45 nm CMOS technology with a power-supply voltage of 1 V. Keywords: Power consumption, Propagation delay, Quantitative analysis, RTD-loaded NMOS inverter, Voltage-transfer characteristic

Proposed wide dynamic-range controllable current sources

Generating ultra-low currents using resistors is impractical especially in integrated circuits due to the wasting of much area associated with the required very large resistors. In this paper, three ultra-low current sources that are suitable for biomedical and implantable applications are proposed. The generated currents are in the nanoampere range. One of the proposed current sources depends on a modification of the conventional Widlar MOS current source in which a tunable subthreshold-region operated transistor is utilized as a controlled resistance. The proposed current source is suitable for low-voltage and low-power applications. Also, two digitally controlled current sources (DCCSs) are proposed. The DCCSs find a wide variety of applications in digital-to-analog converters, implantable microstimulators, and charge pumps. The three proposed current sources are analyzed quantitatively. They are also verified by simulation adopting the 45 nm CMOS Predictive Technology Model (PTM) with a power-supply voltage, VDD, equal to 1 V